1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing method thereof and, more particularly, to a semiconductor device in which a resistance of a polysilicon interconnection and a contact resistance of an interconnecting portion thereof are reduced, and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In recent years, as semiconductor devices such as semiconductor integrated circuit devices have been rapidly developed to be operable with higher performance and higher integration, a reduction in width or spacing of a conductive interconnection layer has also been increasingly required.
In order to achieve the reduction in width or spacing of the conductive interconnection layer, materials having lower resistivities need be employed for conductive interconnections as well as an enhanced technique of forming a more miniaturized conductive interconnection layer. As means for forming a miniaturized conductive interconnection layer, a polysilicon interconnection layer is employed which is made conductive by forming a polycrystalline silicon layer on an insulator film and then doping impurity ions such as phosphorus or boron into the formed polycrystalline silicon layer. To meet a demand for the reduction in resistivity for higher integration, as a technique has also been developing as to form a refractory metal layer such as tungsten, molybdenum or titanium on a surface of a polysilicon layer, then react this refractory metal layer with the polysilicon layer and form a conductive interconnection layer of refractory metal silicon.
As a method of forming a metal silicide layer, such a method can also be considered in which silicide is directly formed by sputtering or a CVD method. The sputtering is a method of sputtering metal atoms such as of titanium and silicon atoms to be adhered onto an insulator film and simultaneously react the atoms with each other, thereby to form a metal silicide layer having a thickness of submicron. By this method, however, in case of forming the metal silicide layer in a space having a high aspect ratio such as a contact hole, it is difficult to form the metal silicide layer which sufficiently fills the contact hole because the atoms do not distribute entirely at the bottom of the contact hole. By the CVD method, it is technically possible to form the metal silicide layer directly on the insulator film by reacting a gas containing titanium and the like with silane in vapor phase. This method is, however, still under development and is not practical especially for mass production.
Thus, a method in which a polysilicon layer and a metal layer are separately stacked in sequence and thereafter subjected to silicidation by a heat treatment has conventionally been adopted for formation of a metal silicide interconnection in a semiconductor device.
A description will now be given of a conventional conductive interconnection layer formed of metal silicide, with reference to FIGS. 1A and 1B. FIG. 1A shows a structure for forming a contact and an interconnection having a conventional structure of self-aligned silicide (hereinafter referred to as salicide). Here, the salicide structure means such a structure that only a polysilicon layer formed on an insulator film is silicidized in a self-aligned manner to form a metal silicide layer (refer to U.S. Pat. No. 4,622,735 and so on).
In manufacture of the structure shown in FIG. 1A, an impurity diffusion layer 3 doped with impurity ions such as phosphorus, a gate electrode 4 and an insulator layer 5 are first formed in regions isolated by a field oxide film 2 in the surface of a silicon substrate 1. Then, a contact hole 6 is formed in insulator layer 5 on the region of impurity diffusion layer 3 by etching. Thereafter, polysilicon is deposited in contact hole 6 and on insulator layer 5 by CVD, and unnecessary portions are etched away, thereby forming a polysilicon layer 7. Then, a metal layer 8 is deposited on the surface of polysilicon layer 7 and on the exposed surface of insulator layer 5 by sputtering.
After the structure shown in FIG. 1A is formed in the above-described manner, a heat treatment causes polysilicon layer 7 to react with metal layer 8, thereby to form a metal silicide layer. Then, removal of unreacted metal and a metal compound such as nitride enables formation of a metal silicide layer in a self-aligned manner.
FIG. 1B shows a structure for further forming a metal silicide interconnection layer on a polysilicon interconnection layer through a contact. In the manufacture shown in FIG. 1B, the process to the step of forming polysilicon layer 7 is the same as that shown in FIG. 1A. In this structure, an insulator layer 15 is further deposited on the surface of polysilicon layer 7 and on the surface of exposed insulator layer 5, and a contact hole 9 is made at a predetermined location in insulator layer 15 on polysilicon layer 7 by etching. Thereafter, a polysilicon layer 10 and a metal layer 11 are formed by the same method as the one employed for the formation of polysilicon layer 7 and metal layer 8 in FIG. 1A. A metal silicide layer is then formed by a heat treatment, and then the unreacted metal or metal compound is removed, thereby forming a metal silicide layer in a self-aligned manner.
A resistance value of a junction between the metal silicide interconnection thus formed and silicon substrate 1 or a resistance value of a junction between the metal silicide interconnection and polysilicon layer 7 differs according to the relative relation in thickness between metal layers 8, 11 before silicidized by heat treatment and polysilicon layers 7, 10. The reason for this will be described as follows with reference to FIGS. 2-5B.
FIG. 2 shows a state before a heat treatment is carried out for insulator layer 5 formed on silicon substrate 1 and having contact hole 6, polysilicon layer 7 deposited on the surface of insulator layer 5 and metal layer 8 formed on the surface of polysilicon layer 7 to cause silicidation. Based on the relative relation in thickness between polysilicon layer 7 and metal layer 8 in this state, the vicinity of the junction between silicon substrate 1 and the metal silicide layer silicidized by heat treatment provide the following three different states.
(1) When a heat treatment for silicidation starts in the state shown in FIG. 2, the silicidation advances from an interface between metal layer 8 and polysilicon layer 7 both upward and downward. Thus, when the thickness of metal layer 8 is sufficiently smaller than that of polysilicon layer 7, the heat treatment silicidizes the entire metal layer 8 and also leaves unreacted polysilicon layer 7 at lower portions. This causes polysilicon to come into contact with silicon substrate 1 at the bottom of contact hole 6 (see FIG. 3A). In this state, an equivalent circuit of resistance between the surface of a metal silicide layer 12 and that of silicon substrate 1 is shown in FIG. 3B. Referring to FIG. 3B, a symbol Rs denotes a resistance value of metal silicide layer 12 and Rp denotes a resistance value of unreacted polysilicon layer 7. PA1 (2) In case where the relative relation in thickness between metal layer 8 and polysilicon layer 7 is appropriately set so that the silicidation of these layers is simultaneously completed over the entire thickness of both layers due to heat treatment, the layers become a state shown in FIG. 4A after heat treatment. That is, metal layer 8 and polysilicon layer 7 are both silicidized to form metal silicide layer 12. An equivalent circuit of resistance between the surface of metal silicon layer 12 and that of silicon substrate 1 in this case is shown in FIG. 4B. PA1 (3) When the thickness of metal layer 8 is sufficiently larger than that of polysilicon layer 7, the entire polysilicon layer 7 is silicidized to become a portion of metal silicide layer 12. The metal layer 8 is also silicidized from the lower portion thereof to become metal silicide layer 12; however, after polysilicon layer 7 is all silicidized, the silicidation due to the reaction between metal layer 8 and polysilicon layer 7 stops, thereby leaving unreacted metal layer 8 in the vicinity of the surface. Thereafter, a portion of the metal in this unreacted metal layer 8 enters silicon substrate 1 through a junction (hereinafter referred to as a contact portion) between metal silicide layer 12 at the bottom of contact hole 6 and the surface of silicon substrate 1 and then silicidizes silicon substrate 1. Also, the silicon in silicon substrate 1 is suctioned upward through the contact portion, so as to silicidize unreacted metal layer 8. With these reactions proceeding, there occurs a deficiency of silicon at the interface between a silicide layer 12a produced in silicon substrate 1 and unreacted silicon substrate 1. If air gap is produced or impurities deposit at the deficient portion, an insulator layer 13 is formed (see FIG. 5A). An equivalent circuit of resistance between unreacted metal layer 8 and silicon substrate 1 in this state is shown in FIG. 5B. In the figure, a symbol Ri denotes a resistance value of insulator layer 13.
For each case of (1), (2), (3), each total resistance value of the interconnection and the contact portion will now be described with reference to each equivalent circuit diagram (FIG. 3B, 4B, 5B). In the case of (1), a resistance value between the surface of metal silicide layer 12 and that of silicon substrate 1 becomes a series connection of R.sub.s, and R.sub.p, i.e., R.sub.s +R.sub.p. A resistance value between metal silicide layer 12 and the surface of silicon substrate 1 is Rs in the case of (2), while a resistance value between metal layer 8 and silicon substrate 1 becomes a series connection of R.sub.s and R.sub.i, i.e., R.sub.s +R.sub.i in the case of (3).
Assuming that the resistance value Rs of metal silicide layer 12 is equal in all the cases of (1), (2), (3), an inequality R.sub.s &lt;R.sub.s +R.sub.p &lt;&lt;R.sub.s +R.sub.i is given, and thus the minimal resistance value can be obtained in case where the (2) case (FIG. 4A) is implemented.
This result is also exhibited by a change in sheet resistance in case where the initial thickness of polysilicon is 1000 .ANG. and polysilicon layer 7 is partially or entirely silicidized by the foregoing process, as shown in FIG. 6. More specifically, the sheet resistance of polysilicon which is not silicidized at all is several 100.OMEGA./.quadrature., whereas the sheet resistance becomes decreased as the film thickness of silicide becomes increased and then attains a lower resistance value of approximately 1.OMEGA./.quadrature. when all the polysilicon is silicidized.
Meanwhile, in case where the excessive amount of metal remains unreacted, as shown in FIG. 5A, insulator layer 13 is formed at the contact portion between metal silicide layer 12 and silicon substrate 1, resulting in a higher resistance. The change of a resistance value (hereinafter referred to as a contact resistance value) at a junction at the bottom of the contact hole from the state of FIG. 2 to the state of FIG. 5A in the case of (3) is shown in FIG. 7, which is a graph where the abscissa indicates the elapse of heat processing time, while the ordinate indicates the contact resistance value. According to this graph, the contact resistance value in case where only a portion of polysilicon layer 7 is silicidized as compared with the initial polysilicon layer 7 is approximately constant at a value a little less than 1.times.10.sup.-6 .OMEGA..cm.sup.2, whereas the contact resistance value sharply increases when the time point when the entire polysilicon layer 7 is silicidized (a time point T.sub.1 in the graph of FIG. 7) has passed.
As described above, all the polysilicon layer 7 need be silicidized just completely as shown in FIG. 4A in order to minimize the series resistance of the conventional contact portion and of the interconnection silicidized in a self-aligned manner. In addition, if the metal layer is slightly thicker than the case shown in FIG. 4A, insulator layer 13 of a higher resistance is formed, while if metal layer 8 is thin, unreacted polysilicon layer 7 having a higher resistance than that of the metal silicide is interposed in the contact portion. It is impossible to constantly obtain the minimum series resistance in view of difficulties in precisely controlling the film thickness of metal layer 8 and polysilicon layer 7.